Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions. in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically comprises source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide laver therebetween. The gate electrode controls the turn-on and turn-off of each transistor.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate, and depositing a barrier nitride layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality. The trench is then refilled with an insulating material (or "trench fill"), such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP) using the barrier nitride layer as a polish stop, and the nitride and pad oxide are stripped off the active areas to complete the trench isolation structure.
When creating the STI structure, it is considered desirable for the uppermost surface of the substrate to be flush (i.e., coplanar) with the uppermost surface of the trench fill, in order to maximize the performance of the finished device, and to provide a flat topography for subsequent processing steps, particularly photolithographic processing, thereby facilitating the formation of small features with accuracy and increased manufacturing throughput. However, planarity is adversely affected by conventional techniques, primarily due to the application of the barrier nitride laver as a polish stop.
Referring to FIGS. 1A-1C, which illustrate the substrate 1, pad oxide layer 2, barrier nitride layer 3, oxide liner 4 and insulating material 5, after the insulating material 5 has been applied (FIG. 1A), and planarized using the barrier nitride layer 3 as a polish stop (FIG. 1B), the barrier nitride layer 3 and pad oxide layer 2 are stripped off (FIG. 1C), creating a step having a height S between the main surface 1a of the substrate 1 and the uppermost surface 5a of the insulating material 5. Thus, the use of a conventional barrier nitride layer 3 as a polish stop creates a topographical step preventing planarity at the interface of the surface 1a and the surface 5a. Such a topographical step renders it difficult to photolithographically process subsequent layers of the device, particularly in forming features with fine dimensions, thereby adversely affecting process yield and production cost. This problem becomes more acute as circuit geometry is continuously reduced.
There exists a need for a semiconductor device and a method of manufacturing a semiconductor device wherein the uppermost surface of the substrate or epitaxial layer is substantially flush (i.e., coplanar) with the uppermost surface of the trench. thereby facilitating the formation of subsequent layers of the semiconductor device and enabling photolithographic processing of fine features. There also exists a continuing need for simplified shallow trench isolation methodology with fewer processing steps, thereby increasing manufacturing throughput.